Industrial Informatics and Signal Processing Research Group

On-chip FLIM processing

nlike the low optical gain CCD based sensors, a SPAD diode, when biased at above its breakdown voltage, can be triggered by a photon that results in a self-sustaining avalanche multiplication process. Its gain is so massive that its output current can be easily converted into a digital signal without using complex front-end amplifiers deteriorating the signal-to-noise (SNR) ratio. With such single photon sensitivity, SPADs are suitable for photon-starved applications such as single molecule detection. The latest efforts to miniaturise the pixel size have allowed the development of much larger SPAD arrays. Besides, the photon count rate of the latest developed SPADs can easily exceed hundreds of kHz. As a result, the very high throughput data available from the new SPAD systems, however, poses a major challenge in the design of the readout architecture. We aim to develop on-chip imaging processors to compress the data on-chip and reduce the readout bandwidth limitations.  The figure below shows a 160x128 SPAD pluse in-pixel stop-watch arrays.

Figure 1 below.  

SPAD array 160x128 0.13um CMOS SPAD plus in-pixel time-to-digital converters.

 

References:

Veerappan, C., Richardson, J., Walker, R., Li, D., Fishburn, M. W., Maruyama, Y., et al. (2011). A 160x128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter. Paper presented at the Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 312-313. (http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5746333)