Thermal Control

It would be possible to vary the temperature of an FPGA during or in-between fitness trials. That was not adopted here in case the rapidly repeated thermal cycling would lead to premature chip-failure. Instead, the FPGAs are held at at different but constant temperatures.

Fig. 4 shows the present arrangement for the cold FPGA. A wafer-like Peltier-effect thermoelectric cooling device is used , which can pump heat from one face to the other at up to 68.8W [6,5]. Its cold side is attached to the top face of the chip package, and the hot side to a heatsink. For low FPGA temperatures, good thermal insulation between chip and heatsink is required; this is aided by the copper spacing block. The FPGA package should also be insulated from the surroundings as much as possible to minimise `heat leak.' For this reason, unused pins of the FPGA's socket are not soldered into the circuit-board. To obtain low temperatures, the heatsink must be very effective: a $0.14^{\circ}$C/W part was used, with additional forced-air cooling.

  

Figure 4: Arrangement for the cold FPGA. The proportions of the main components are drawn to scale. (a) Ceramic FPGA package, (b) silicon die within, (c) copper spacing block, (d) Peltier-effect heat-pump, (e) thermal fuse, (f) large cuboid fan-cooled heatsink, (g) foam thermal insulation. The LM35CZ temperature sensors, and the fuse, are mounted in epoxy resin. Heat-transfer paste is applied at all thermal interfaces.

The PC reads the value of a temperature sensor attached to the chip package, and in response provides an appropriate control voltage for the heat-pump. A standard proportional+derivative (PD) linear feedback control system is implemented in software, which attempts to hold the measured temperature at a given set-point. This was found to cope well with the various nonlinearities and time-delays present in the system.

If worked too hard (by attempting to cool too rapidly, or maintain too low a temperature for the current ambient temperature), the thermoelectric device enters a highly inefficient region of its operating characteristics, and converts a lot of electrical energy to heat. In this situation the chip temperature will rise, the PD controller will increase the pump power further, and thermal runaway will occur; the controller will not recover even if the original cause - such as an unusually large rise in lab temperature - is removed. For this reason, a rather conservative `overdamped' controller is used. Before an evolutionary experiment, it spends 40 minutes gradually lowering the chip to the setpoint temperature, which is achieved without overshoot. Nevertheless, it is able to keep the chip package temperature to within $\pm1^{\circ}$C during the experiment (even as ambient temperature and FPGA power dissipation vary), with the state of the controller being updated every 30s. Evolving circuits can be prone to interference from nearby fluctuating signals, so the controller state is always updated between, not during, fitness evaluations.

The hot FPGA is thermostatically regulated in the same manner as the cold one described above, with the heat-pump connected in reverse. For the hot chip, it is less important to keep the thermoelectric device at an efficient operating point, so only a much smaller heatsink is needed. On a third FPGA, a constant thermal gradient is maintained by using a combination of heating and cooling pumps. By using a single large heatsink shared by the two pumps, there is a thermal cycle: one pump is heating the heatsink and the other cooling it. This makes it relatively easy to operate the thermoelectric devices efficiently at high power, so a surprising large thermal gradient can be maintained across the chip.

The three thermally regulated XC6216's were chosen in the Xilinx 299-pin pin-grid-array package. Unlike most IC packages, these are assembled `Cavity Down', with the silicon die attached to the inside top of the package, for optimal heat transfer between the die and the upper surface of the case [12, chap. 10]. Thus the thermal regulation apparatus will have a very direct influence on the temperature of the silicon.

With lab temperatures rising up to $25^{\circ}$C during the day, the set-point of the cold chip is currently set at $12^{\circ}$C during an evolutionary experiment. In the Mk. II Evolvatron (under development), the circuit-board with the cold FPGA will be in a plastic bag with some desiccant, and simply placed in a domestic freezer. This will allow lower chip temperatures even for hotter (summer-time) lab conditions. The Peltier-cooling arrangement will be retained on another device for more precise temperature control for analysis purposes. For brief, imprecise, low-temperature tests (i.e. not during evolution), standard electronics freezer spray can also be used ( $\sim-50^{\circ}$C), or even liquid nitrogen ( $-196^{\circ}$C).

The hot FPGA is run at a case temperature of $60^{\circ}$C. A greater temperature could easily be maintained, but long-term time-to-failure must be considered, along with a margin for error. The FPGA with a thermal gradient is run with one of the temperature sensors at $30^{\circ}$C and the other at $15^{\circ}$C. The silicon die is approximately 1cm², so these sensors are attached across the central region of the top surface of the case, with a separation of  1cm. The resulting thermal gradient of $15^{\circ}$C/cm is about the maximum that could reliably be obtained using the components chosen.