The Operational Envelope

The following parameters of the operational envelope are present:

Electronic surroundings. Four of the FPGAs are in separate metal boxes, configured by the PC via their serial interfaces. Most of the pins of these FPGAs are unused and unconnected. The FPGA on the PCI card is configured via its parallel interface, and nearly all of its pins are connected to support various features of the PCI card not used here.

Circuit position on FPGA. The $10\times 10$ circuit being evolved is placed in a different position on each $64\times64$ FPGA. It is possible that adjacency to edges or corners of the array would affect the circuit, so the aim is to provide a variety of such conditions.

FPGA fabrication variations. Two of the devices are early engineering samples of the XC6216 made at a Yamaha foundry, and the remaining three are the current production version fabricated by Seiko.

Packaging. Three of the devices are in 299-pin ceramic pin-grid-array packages (`PG299'). Another has a plastic 84-pin PLCC package (`PC84'). The remaining chip, on the PCI card, is surface-mounted in a 240-pin plastic PQFP-type package (`HQ240'). This package contains a grounded nickel-plated copper heatsink slug in very close proximity to the silicon die. See [12, chap. 10] for packaging details.

Temperature. Two of the FPGAs are at the ambient temperature of the lab (17- $25^{\circ}$C). Another is maintained at a constant $60^{\circ}$C, and another at $12^{\circ}$C. Finally, a further chip has a thermal gradient of $15^{\circ}$C/cm maintained across the central region of the package in which the die is located. See 5.2 for details.

Power supply. The FPGA on the PCI card is running on the same power supply as the rest of the PC, as usual. Two of the other devices are powered by the 5V output of a separate typical computer switch-mode power supply unit (PSU), which is also running (from a different output) the numerous 12V fans involved in thermal regulation. The remaining two devices are powered by a precise programmable PSU, with one chip at 4.80V and the other at 5.20V.

Load. In this series of experiments, only one pin on each FPGA is configured as a user output from the evolving circuit. Each of these drives approximately 70cm of audio-grade cable with a co-axial shield, before reaching an integrator (housed in a separate shielded box) used to measure average voltage. The integrator design used presents an almost purely resistive load impedance of approximately 350k$\Omega$. To provide some variation, a 100k$\Omega$ resistor to 0V was connected to the output of one of the FPGAs close to the chip.

  

Figure 3: Variations within the operational envelope: Evolvatron Mk. I