Questions to be Addressed

Of the many issues on the research agenda, the following are primary:

• What resources are needed for robustness? Are stable off-chip components required? Is it necessary to provide a stable oscillation as an extra input to the evolving circuits? Such a clock would be a resource, to be used in any way (or ignored) as appropriate, rather than an enforced constraint on the system's dynamics as in synchronous design.
• Can generalisation over an entire, practical, operational envelope be achieved through evolution in a relatively small number of different conditions?
• Given the experimental arrangement described herein, is the evolution of a robust circuit more difficult than of a fragile circuit evolved on just one FPGA? (An apparently harder task is not necessarily more difficult for evolution, depending on the pathways available for evolutionary change.) Does it make sense gradually to increase the diversity and span of the operational envelope during evolution, or should the population be exposed to a representation of the complete operational envelope right from the beginning?
• If robust circuits are evolved, how do they work? Do they look more like conventional circuits? Are they still considerably more efficient?