Evolutionary algorithms have been successfully used to design electronics previously, but either temporarily ignoring the need for robustness (eg. [8,4]), or constraining the available choice of components, component values, and interconnection topologies, such that all expressable circuits are guaranteed to be adequately robust (eg. [1,7]). In contrast, the current work continues the development of `unconstrained intrinsic hardware evolution', whereby evolution is given maximal freedom to exploit the full repertoire of behaviours that a physical reconfigurable VLSI device (such as an FPGA) can produce. Conventional design principles are not enforced, in the hope that forms and processes that are `natural' to the VLSI medium and the evolutionary algorithm can result. Earlier experiments have shown that circuits so evolved can operate in very unusual ways, yet be impressively compact by putting to use more of the rich dynamics and interactions of the silicon components -- possibly even including subtle aspects of semiconductor physics.
An example is shown in Fig. 1.
This circuit was evolved using a standard genetic algorithm to discriminate
between 1kHz and 10kHz audio tones: the fitness function was to maximise
the difference in average output voltage as bursts of the two different
inputs were applied. Of the
area of a Xilinx XC6216 FPGA provided ,
perfect behaviour was achieved using only 32 cells, as shown. There was
no clock, and no external timing components, so to discriminate between
input periods of 1ms and 0.1ms using so few components, each having timescales
a factor of 105shorter, is remarkable: a human designer would
use more. It was shown that the rich dynamics and detailed physics of the
VLSI medium were exploited to a high degree in achieving this efficiency.
This experiment is built-upon later in the paper, and the reader is referred
to  for full details and 
for an evolution-theoretic analysis.
Such early evolved `unconstrained' circuits, though exciting and informative, are practically useless. Their operational envelope is inadequate for any real-world application, given the present norms and expectations of industry. Most notably, they only work properly in a narrow temperature range, and only on the particular FPGA chip used to instantiate them for fitness evaluation during evolution. To be most useful, the configurations should work on any FPGA chip of the same nominal specification (even though no two are absolutely identical), and preferably over a large temperature range. Then the user could purchase or licence the configuration (perhaps over the internet), obtain an appropriate FPGA from a local supplier, and use the evolved circuit in a product. Similar use of proprietary `macros', `cores' or `intellectual property' (IP) as parts of a larger design on an FPGA is already well established in industry. Realistically useful behaviours have been successfully evolved (eg. the above 1010 configuration was further evolved to distinguish between audio signals for the spoken words ` GO' and ` STOP'), but will remain lab curiosities until they can work reliably on other people's FPGAs of the same type.
This paper describes the beginning of an attempt to evolve such robust unconstrained circuits by physically exposing the evolving circuits to samples of the operational envelope during fitness evaluations. Robustness is as much part of the problem to be solved as the behavioural specification: a non-robust circuit simply will not work for part of its evaluation. Evolution is free to find a means to robustness tailored to the particular task, and to the physical resources available in the VLSI medium. Because the need for robustness is integrated with behavioural requirements, it can exert an influence at all stages during the evolution of the circuit (not just in a final `implementation' step). Thus it is hoped the impressively effective exploitation of silicon properties seen previously will still be possible whilst meeting robustness requirements.  identifies possible mechanisms for robustness, drawing analogies with nature.
After clarifying the objectives, the main part of this paper is devoted to showing the technical feasibility of providing a selection pressure for robustness within intrinsic hardware evolution. Promising early results are then described. The modest aim of the paper is to share thoughts and experiences, to aid future research within the evolutionary electronics community.